[Edaily Reporter JAEMIN SONG ] SK hynix has unveiled a roadmap for “CPO (Co-Packaged Optics),” a next-generation optical interconnect technology that transmits data between semiconductor chips using light. The company is seeking to secure technology that will resolve data bottlenecks not only in High Bandwidth Memory (HBM) but also across entire artificial intelligence (AI) systems.

SK hynix announced on the 20th that it had published a paper titled “CPO Technology for High-Performance Computing and Artificial Intelligence,” co-authored with a global research team, in the international academic journal *Nature Electronics*. Hong Seung-hoon, Team Leader of the AI Infrastructure Team at SK hynix, and Lee Kyu-sang, a professor in the Department of Electrical and Computer Engineering at the University of Virginia, served as corresponding authors. Researchers from the University of Illinois at Urbana-Champaign, Nanyang Technological University, the Massachusetts Institute of Technology (MIT), and Yonsei University also contributed to the study.

CPO is a technology that integrates optical transceivers into the same package as the processor, enabling data to be exchanged between chips using light instead of electrical signals. Conventional copper wiring suffers from increased signal loss and power consumption as connection distances lengthen and transmission speeds increase. In contrast, CPO minimizes the distance electrical signals must travel, thereby improving data transmission speed and power efficiency.

While the computational performance of AI accelerators is increasing by about threefold every two years, the interconnect bandwidth linking chips has only increased by about 1.4 times over the same period. As massive AI clusters connecting thousands of graphics processing units (GPUs) and HBM spread, the “bandwidth barrier”—where the speed of data transfer between systems limits overall performance rather than the performance of the chips themselves—is growing, according to the explanation.

The research team proposed the following goals for implementing next-generation AI infrastructure: bandwidth of over 100 terabits (Tb)/s per node, energy consumption of less than 1 picojoule (pJ) per bit, and inter-chip latency of less than 10 nanoseconds (ns). They also outlined a technological roadmap progressing from 2D packaging to 2.5D interposers and 3D heterogeneous integration, along with the challenges that must be addressed for commercialization.

In the long term, the company envisions expanding optical interconnects to include memory interfaces. By directly connecting processors and memory via optical interposers, multiple AI accelerators can share large-scale memory resources. Through this, SK hynix plans to broaden its role as a memory supplier from individual products, such as HBM, to the design of AI systems at the rack and pod levels.

Professor Lee stated, “Even if the performance of computing chips improves, the overall system performance cannot increase if the data transfer capability between chips cannot keep up,” adding, “Technology that transmits data using light instead of copper wiring is the most promising path for expansion.”

Team Leader Hong remarked, “Memory companies are also evolving beyond simply supplying individual products to become partners that help build the overall competitiveness of customers’ AI systems.”