[Edaily Reporter JAEMIN SONG ] SamsungElectronics has unveiled its next-generation V10 BV-NAND flash, which features significantly improved bit density and I/O performance. Compared to the previous generation, bit density has increased by more than 58%, data I/O speeds have improved by more than 33%, and power consumption has been reduced by more than 25%.

On the 31st, SamsungElectronics disclosed the development background and key technologies of the V10 BV-NAND through its semiconductor newsroom. The V10 recently received the “3D NAND Innovation Award” at “FMS 2026,” held in the United States.

The V10 is the latest 3D NAND flash developed to meet the rapidly growing demand for high-performance, high-capacity, and low-power storage in the AI era. Based on a V-NAND structure utilizing 3D bonding technology, it features over 400 word lines (WLs).

Bit density—the amount of data stored per unit area—has been increased by more than 58% compared to the previous generation. Input/output (I/O) speed has improved by over 33% to more than 4.8 Gbps, while power consumption has been reduced by more than 25%.

Shin Ji-yeon, Team Leader (TL) of the Product Planning Team at SamsungElectronics, said, “The V10 was developed to meet the demands for high-performance, high-capacity, and low-power storage in the AI era,” adding, “It can support the implementation of ultra-high-capacity 128 terabyte (TB) solid-state drives (SSDs) and next-generation PCIe 7.0 SSDs.”

SamsungElectronics focused not merely on increasing the number of stacked layers and capacity, but on simultaneously achieving high integration, high performance, and low power consumption. This is because, as data processing volumes in AI systems have increased, the demand for storage capacity and bandwidth has grown, and power consumption has emerged as a key factor determining the total cost of ownership (TCO) for data centers.

To achieve stacking of over 400 layers, the company applied “3-stack”-based HARC merging technology, which involves dividing the cell into three parts for manufacturing and then connecting them vertically. By combining multi-hole and zero-dummy-hole technologies, the company increased integration density while keeping the number of process steps and manufacturing costs in check.

The company also introduced wafer bonding technology, in which the cell and peripheral circuits are fabricated on separate wafers and then vertically bonded. According to the company, designing the cell and peripheral circuits independently allows for improved peripheral circuit performance and a reduction in chip size.

Jeong Da-un, a Project Leader at SamsungElectronics’ Flash Development Lab, explained, “While implementing ultra-high-layer V-NAND with over 400 layers, we had to simultaneously address the increase in process steps and manufacturing costs, as well as the rising complexity of the process.” He added, “We secured both integration density and manufacturing efficiency through HARC merge, multi-hole, and zero dummy-hole technologies.”

To enhance I/O performance, the company improved the transistor characteristics of the peripheral circuits and applied technology to separate command and address signals. It also reduced signal interference that occurs during high-speed data transmission, achieving I/O speeds of 4.8 Gbps or higher.

To reduce power consumption, the company lowered the supply voltage of the peripheral circuits and adopted a structure that directly utilizes an external power source. It also introduced technologies to reduce the power consumed during wordline charging and discharging, as well as during high-speed I/O operations.

Issues such as wafer warpage and reduced cell reliability—which arise as the number of stacking layers increases—were also addressed. By precisely controlling multiple stacking layers, the voltage applied to unselected layers during write operations was reduced by more than 70%, and the bit error rate was improved by 4%.

Park Sang-soo, Project Leader at SamsungElectronics’ Flash Development Lab, said, “This award is significant because it recognizes that we have simultaneously solved the three major challenges demanded by the AI era: high integration, high performance, and low power consumption.”