Samsung and Ambarella Form 2-NANO Alliance to Develop Physical AI Chips
Ambarella Developing Edge AI Platform Based on Samsung’s 2-Nanometer Technology
Margaret Han, Former TSMC Executive Vice President, Expands Connections Within the North American AI Ecosystem
Stepping Up Efforts to Secure 2-Nanometer Customers… Samsung Accelerates Push into North American Fabless Market
[Edaily Reporter SOYEON KIM ] Samsung Foundry (semiconductor contract manufacturing) is expanding its customer base by leveraging its cutting-edge 2-nanometer (nm) process. The company is accelerating its push into the North American market by expanding its reach into the physical artificial intelligence (AI) sector. Margaret Han, Senior Vice President of Foundry Operations at SamsungElectronics’ North American Semiconductor Division (DSA) and a former TSMC executive, is personally leading efforts to secure customers by building connections with the local physical AI ecosystem.
According to industry sources on the 15th, SamsungElectronics and AI semiconductor design firm Ambarella are developing a next-generation edge AI platform using the cutting-edge 2-nanometer process. These AI semiconductors are designed for physical AI systems that operate in the real world, such as those embedded in robots, drones, and autonomous machines. The goal is to process AI computations and data from multiple sensors in real time while consuming low power.
A SamsungElectronics semiconductor factory currently under construction in Taylor, Texas. (Photo: SamsungElectronics) Chan Lee, Chief Operating Officer (COO) of Ambarella, stated, “We are developing a next-generation edge AI platform by leveraging Samsung Foundry’s 2-nanometer technology and Cadence’s PCIe 5.0 IP,” adding, “This has enabled us to implement AI computations and multi-sensor processing at low power while also streamlining the design and verification processes for the 2-nanometer chips.”
Through collaborations such as this one with Ambarella, SamsungElectronics is securing reference designs that expand the application of its 2-nanometer process from existing high-performance computing (HPC) and AI chips to the edge AI sector. Samsung Foundry’s 2-nanometer Gate-All-Around (GAA) process is focused on simultaneously delivering the high performance and low power consumption required for AI semiconductors. By improving the transistor structure and flexibly applying nanosheet configurations, the process enhances computational performance and power efficiency.
In particular, for sub-2-nanometer processes, the competition is shifting beyond simply miniaturizing transistors to managing the overall complexity of semiconductor design and packaging—including chiplets, 3D-ICs, and high-bandwidth interconnects. SamsungElectronics’ strategy is to meet the diverse needs of its AI semiconductor customers by leveraging its competitiveness in the 2-nanometer process.
SamsungElectronics is stepping up its efforts to secure customers by expanding its engagement with the AI semiconductor ecosystem in North America. Vice President Han spent over 20 years at TSMC. Samsung recruited him from outside the company to strengthen its competitiveness in the North American foundry market. Recognized as one of the semiconductor industry’s leading experts in global strategy and sales, he is responsible for expanding cooperation with North American clients.
Ambarella is hosting a private networking reception at the “AI Infrastructure Summit,” taking place over three days starting today (local time) at the Santa Clara Convention Center in California. The event will feature Vice President Han, along with chief technology officers (CTOs) from major tech companies such as Google. Vice President Han’s participation in the panel is seen as a move to expand collaboration with fabless companies and big tech firms, including Ambarella, in the North American market and to broaden the customer base for SamsungElectronics’s 2-nanometer process.Key Details of SamsungElectronics and Ambarella’s AI Collaboration
SamsungElectronics’ Taylor Foundry plant, the company’s U.S. manufacturing hub, is set to begin operations. SamsungElectronics recently held a ceremony to mark the arrival of equipment and is currently preparing for operations, including trial runs, with the goal of launching by the end of the year.
In the future, SamsungElectronics’ Taylor foundry will produce products using the company’s next-generation 2-nanometer and 4-nanometer processes. The 2-nanometer process is expected to be used for mass production of SamsungElectronics’ mobile application processor (AP), the Exynos 2600, as well as Tesla’s AI chips, the “AI5” and “AI6.” The industry anticipates that revenue from AI chips for Tesla will begin to be reflected in full starting next year.
An industry official stated, “SamsungElectronics is gradually securing 2-nanometer clients and strengthening its market presence,” adding, “As the AI semiconductor market expands—including physical AI—we will see a gradual improvement in foundry performance.”
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