According to industry sources on the 1st, Choi Jang-seok, Executive Vice President and Head of the Product Planning Team at SamsungElectronics’ Memory Business Division within the Device Solutions (DS) Division, presented the CUBE strategy at Semicon Taiwan 2026 to overcome the limitations of memory technology.
The CUBE strategy represents a vision to strengthen competitiveness in memory technology by advancing four key technical capabilities: △Capacity △Utilization △Bandwidth △Efficiency (power and thermal efficiency). Senior Vice President Choi explained, “With 3D technology, the key is not simply stacking layers, but how each layer is utilized,” adding, “SamsungElectronics is optimizing the placement of logic and memory to reduce data processing latency.”
SEMICON Taiwan is an international semiconductor exhibition where the latest technologies—ranging from semiconductor design and manufacturing to testing and packaging—are showcased, organized by the Semiconductor Equipment and Materials International (SEMI). This year’s event kicked off in earnest on the 1st with major forums and keynote speeches.
Under the theme “Powering the AI Era Through 3D Integration,” Executive Vice President Choi introduced SamsungElectronics’ next-generation memory technologies, including zHBM, zNAND-O, and 3D packaging technologies. Notably, zHBM goes beyond the conventional method of placing High Bandwidth Memory (HBM) next to an AI accelerator; instead, it vertically stacks HBM on top of the AI accelerator. The key lies in reducing the data transfer distance between the AI accelerator and memory by stacking HBM directly on top of the graphics processing unit (GPU), thereby increasing bandwidth and power efficiency.
zHBM aims to deliver △8 times the performance, △3 times the performance per watt, and △a 75–90% reduction in thermal resistance compared to HBM4E. SamsungElectronics has continuously advanced capacity, bandwidth, power efficiency, and thermal management technologies with each generation, from HBM2 through HBM4E to HBM5. The company is accelerating its technology development to meet the growing demand for AI computing.
Executive Vice President Choi stated, “By drastically reducing the distance between dies, we can create a vertical highway that dramatically improves bandwidth,” adding, “The ultimate goal of 3D technology is to reduce the energy required to move a single bit of data.” He further emphasized, “SamsungElectronics is maximizing performance per watt by enhancing structural efficiency.”
SamsungElectronics is also accelerating efforts to strengthen its leadership in the memory market, leveraging the industry’s largest production capacity. The company leads the memory market, holding the top global position in both the DRAM and NAND flash markets. According to market research firm Counterpoint Research, SamsungElectronics ranked first in the global DRAM market in the second quarter of this year with a 39% market share based on revenue. SK hynix and Micron followed with 26% and 25%, respectively. In the NAND flash market as well, SamsungElectronics took the top spot with a 29.3% market share, recording revenue of approximately $23.06 billion in the second quarter of this year.
SamsungElectronics’ massive production capacity is considered a key factor in maintaining its competitiveness in the memory market. Market research firm Omdia forecasts SamsungElectronics’ DRAM production capacity this year at approximately 8.175 million 300mm wafers annually. This figure significantly exceeds that of SK hynix (approximately 6.66 million wafers) and Micron (approximately 3.6 million wafers). In the NAND flash sector as well, SamsungElectronics’ wafer production volume this year is expected to reach approximately 4.77 million wafers, far surpassing that of SK hynix and Solidigm (approximately 2.79 million wafers).