[Edaily JAEMIN SONG Reporter] SK hynix has been named “Partner of the Year” for the second consecutive year in recognition of its successful joint validation of HBM5—the next-generation high-bandwidth memory (HBM)—with Taiwan’s TSMC’s cutting-edge packaging technology.

SK hynix announced on the 28th that it participated in the “TSMC Open Innovation Platform (OIP) Conference” held in Santa Clara, California, on the 23rd (local time) to introduce its next-generation artificial intelligence (AI) memory products and development strategies.

OIP is an open innovation platform operated by TSMC to jointly develop technologies and collaborate with companies in the semiconductor ecosystem. SK hynix has been participating in related forums since 2024 to showcase AI memory technologies developed in collaboration with TSMC.

At this event, SK hynix received the “Partner of the Year” award in the “3D Fabric-HBM Integration” category in recognition of its collaborative achievement in validating HBM5 based on TSMC’s 2.5-dimensional advanced packaging technology, “Chip-on-Wafer-on-Substrate (CoWoS).” This marks the second consecutive year the company has won the award, following last year’s victory.

With each new generation of HBM, the number of stacking layers and data processing speeds increase. To achieve this performance in actual AI accelerators, advanced packaging technology—which connects HBM to components such as graphics processing units (GPUs) on a single substrate—must also be developed. SK hynix and TSMC have been jointly validating packaging compatibility and performance since the early stages of HBM5 development.

At the exhibition, under the theme “Memory Supporting Large-Scale Intelligence,” the company showcased a product lineup essential for AI infrastructure, ranging from HBM to server DRAM and enterprise solid-state drives (eSSDs).

In particular, the company unveiled NVIDIA’s next-generation superchip, “Verarubin,” equipped with SK hynix’s 12-layer 36-gigabyte (GB) HBM4 and 96GB SOCAMM2. HBM4 rapidly transfers data required for large-scale computations around the Rubin GPU, while SOCAMM2—a low-power DRAM-based memory module for AI servers—serves as the main memory for the Vera central processing unit (CPU).

Also on display were next-generation products such as 12-layer 48GB HBM4E, 16-layer 48GB HBM4, 12-layer 36GB HBM3E, and 192GB SOCAMM2. Among the server DRAM products showcased were a 256GB 3DS RDIMM optimized for AI workloads, a high-bandwidth 128GB MRDIMM, and a 64GB RDIMM manufactured using a 10-nanometer-class 6th-generation (1c) process.

The enterprise SSD exhibition area featured the “PEB210 E1.S,” which supports direct liquid cooling (DLC), and the “PS1101 E3.S,” SK hynix’s first quadruple-level cell (QLC)-based eSSD. QLC is a technology that stores 4 bits in a single NAND flash cell, enabling increased capacity within the same area.

Park Dae-sik, Senior Engineer in charge of PCIe design at SK hynix, who led the technical presentation, projected that the PCI Express (PCIe)-based eSSD market would grow approximately 3.8-fold—from 509 exabytes (EB) in 2026 to 1,933 EB in 2030—driven by the expansion of AI infrastructure. He also predicted that demand for E1.S and E3 standards would grow rapidly as the need for high-capacity, high-density products and improved cooling efficiency increases.

SK hynix is preparing next-generation solutions based on “chiplets”—which divide the traditional single SSD controller into function-specific chips—starting with its 6th and 7th generation PCIe products. The company plans to connect each chiplet via UCIe, a universal chiplet interface, to shorten development time and drive capacity expansion and power optimization.

SK hynix stated, “By receiving the Partner of the Year award for the second consecutive year at the TSMC OIP Conference, we have once again reaffirmed the success of the collaboration between our two companies,” adding, “We will work closely with various partners to create the memory solutions needed for the AI era.”