[Edaily Reporter JAEMIN SONG ] SamsungElectronics will apply a Gate-All-Around (GAA)-based 2-nanometer foundry process to the base die of HBM5, its next-generation High Bandwidth Memory (HBM). Building on the mass production experience gained with the 4-nanometer base die for HBM4, the company plans to significantly boost the operating speed and power efficiency of HBM5.

Koo Ja-heum, Executive Vice President and Head of the Technology Development Office at SamsungElectronics’ Foundry Business Division, stated on the 27th via the SamsungElectronics Semiconductor Newsroom, “HBM5 is expected to require an operating speed increase of more than 50% compared to the previous generation, HBM4E,” adding “We plan to apply a 2-nanometer process with a GAA structure to the HBM5 base die and implement through-silicon vias (TSVs) with even higher integration density,” he added.

The base die is a logic semiconductor located at the very bottom of the HBM stack, responsible for exchanging data between external processors—such as graphics processing units (GPUs) and central processing units (CPUs)—and the stacked DRAM. As HBM’s data processing speed increases, the performance and power efficiency of the base die become increasingly critical.

In particular, with the number of interfaces increasing significantly starting with HBM4, the use of leading-edge foundry processes instead of conventional memory processes has become widespread. SamsungElectronics applied its fourth-generation 4-nanometer foundry process to the base dies of the HBM4, which began mass production shipments in February of this year, and the 12-layer HBM4E product, for which samples were supplied in May.

SamsungElectronics’ 4-nanometer process offers two types of gate pitches and various threshold voltage options, allowing for adjustments to area and performance depending on the product design objectives. The HBM4E base die incorporates both high-density and ultra-high-performance devices to achieve operating speeds of over 14 gigabits per second (Gbps). Power consumption was reduced through the efficient placement of metal interconnect layers, and heat dissipation pathways were also improved.

Vice President Koo explained, “The 4-nanometer 4th-generation process has entered its third year of mass production, and its performance and yield have been thoroughly verified,” adding, “Our competitive edge lies in flexible design options that allow us to adjust speed and area to meet specific product requirements.”

SamsungElectronics also highlighted its ability to handle memory, foundry, and advanced packaging operations all under one roof as a key strength. The HBM core die is produced by the Memory Business Division, while the base die is manufactured by the Foundry Business Division; these are then packaged by the Test & System Package (TSP) organization.

The company explained that collaboration among these business units from the early design stages allows for the simultaneous optimization of speed, power consumption, heat dissipation, and yield, thereby reducing development time and costs. In fact, the HBM4 base die met performance and yield targets from the very first sample thanks to process optimization carried out by a company-wide task force (TF). The time taken from process preparation to achieving these targets was approximately three months.

SamsungElectronics plans to use HBM as a springboard to expand its customer base for leading-edge foundry processes. Following the start of mass production of its first-generation 2-nanometer process in the second half of last year, the company plans to begin mass production of mobile products based on its second-generation 2-nanometer process—which features improved yield and performance—in the second half of this year.

The company is also diversifying its business structure—which had been centered on mobile—to include artificial intelligence (AI) and high-performance computing (HPC), cloud service providers (CSPs), automotive electronics, and robotics. According to SamsungElectronics, since securing an order for 2-nanometer automotive products last year, it has continued to receive orders from multiple AI, HPC, and CSP customers. The 4-nanometer process is also being applied to HBM4 base dies and new LPU products from a U.S. AI company.

The company is also strengthening its one-stop solutions that combine advanced packaging with HBM. To meet the demand for high-speed, low-power data transmission in data centers, it has entered the pluggable optical module (PO) business and is developing technologies based on co-packaged optics (CPO) that utilize leading-edge processes and 3D packaging.

Vice President Koo stated, “Building on the experience gained with 4-nanometer-based HBM4 base dies, we will proactively introduce the 2-nanometer process for HBM5 as well,” adding, “We will expand our application areas to include AI, HPC, automotive, and robotics, and provide process solutions tailored to customer needs.”